So Busy

Well it's the time of year when Engineering Students set up camp at the lab finishing up all their projects before the end of the semester. I spent all of Friday-Early Saturday morning in the computer lab. After a brief rest I then spent most of Saturday in the lab again.

Why?

Because we are having trouble integrating the Pretendo. It turns out the processor control was written in a way that will not synthesize properly on the FPGA. A couple of us with more Verilog experience pointed this out to the processor team and spent the rest of the time advising them on what to fix. We also found some problems in the processor and cache with paths that apparently looped around (it seems the compiler wasn't creating muxes or something). So we worked out some restructured code that will hopefully compile better.

To top everything off our timing sim showed that the cache wasn't making some memory timing contraints. The cache designer went back and will have it fixed by tonight. Hopefully everything will be together by Monday.